Scan chains are a technique used in “Design For Test” to provide a simple way to set and observe every flip-flop in an integrated circuit (IC). By using scan chains, each integrated circuit can be tested to validate that the product hardware contains no defects that could adversely affect the designed functioning of the product.
Tests generally are driven by test programs that execute in Automatic Test Equipment (ATE) such as an automatic test pattern generation (ATPG) tool. The ATPG is an electronic design automation tool used to find an input (or test) sequence that, when applied to a digital circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by a particular fault.
Tests are applied to integrated circuits by loading the IC's scan chains with a test pattern, applying one or more clocks, and then unloading the responses from the scan chains. This process is repeated many thousands, of times, with the length of the longest scan chain typically dictating the number of tester cycles required for loading/unloading scan chains. And, as is known, the test cost is directly related to test time which, in turn, is directly related to the length of the longest scan chain. For example, longer scan chains require longer load and unload times thus increasing the overhead costs.
Given the fact that the test cost is directly related to the test time, it is ideal to minimize the longest scan chain. For this reason, given a fixed number of scan chains, the length of the longest scan chain is typically minimized when all scan chains are of equal length. While it may be impractical to achieve scan chains of exactly equal length, it is desirable to balance the lengths of scan chains such that the maximum length is only a few percent longer than the average length. In one example, scan chains may be considered to be balanced if they are within a 3% variance, e.g., of the average length.
In known implementations, some scan chains may be significantly shorter than average, even zero length, and still result in “balanced” scan chains. For example, a hypothetical design with 100,000 scan cells distributed among 100 scan chains can have 97 scan chains of length 1030, one scan chain of length 90, and two scan chains of length 0, and still have scan chains balanced within 3%. In other words, the longest chain is 3% (1030) larger than the average length (1000).)
Also, until recently, the number of scan chains on an IC was limited by the number of pins available to be used for scan or by the test equipment used for testing the IC. (The number of scan chains was typically 16-32.) However, with the advent of on-chip test data compression and decompression methods, the number of scan chains has increased roughly 20 times. For this reason, it is not unusual to have five or six hundred scan chains; instead of the typical 16-32 scan chains.
Existing tools are capable of generating equal-length scan chains when given complete freedom to apportion scan bits among the available scan chains. However, when some scan bits are already pre-connected into scan segments, and the tool is not given the freedom to break up those pre-connected segments, results are not always optimum. With this noted, hierarchical designs present a particular problem to these tools.
In hierarchical designs, the scan must be inserted into each hierarchical block or module, and then the pre-connected segments are stitched together with top-level scan bits to form chip-level scan chains. That is, scan chains are created for each block and then stitched together to form the chip level scan chains. There are two known processes for attempting to achieve balanced-length scan chains in hierarchical designs, both of which have their shortcomings as discussed below.
In a first process (process “1”), given that the product is specified to have N scan chains, the process will create N near-equal-length scan chains on each hierarchical block. At the top level of the design, the process will stitch the hierarchical block scan chains together and distribute any top-level scan bits equally among the N scan chains This works well for cases where the number of scan bits in each hierarchical block is much greater than N, and when N is not more than a few dozen.
In another process (process “2”), for cases where the number of scan bits in a hierarchical block is not significantly greater than N, the process will create near-equal-length scan chains. In this process, the longest scan chain does not exceed some limit (e.g., 400 scan bits). As long as this limit is small, relative to the total number of scan bits in the entire design, the scan chains can be fairly-well balanced by using known methods at the top level, to stitch scan chains of the hierarchical blocks together to form the desired number of chip-level scan chains.
However, both of these processes (i.e., process “1” and process “2”) require an excessive number of scan pins on each hierarchical block. For example, a hierarchical block with 20,000 scan bits in a design that is to have 500 scan chains would be required to have 1000 scan pins using process “1” or 100 scan pins using process “2” (with a limit of 400 bits per chain).
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.